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DS21Q42 - Enhanced QUAD T1 FRAMER

Download the DS21Q42 datasheet PDF. This datasheet also covers the DS2 variant, as both devices belong to the same enhanced quad t1 framer family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer.

The DS21Q42 contains four framers that are configured and read through a common microprocessor compatible parallel port.

Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store.

Key Features

  • es Four T1 DS1/ISDN.
  • PRI/J1 framing transceivers All four framers are fully independent Frames to D4, ESF, and SLC.
  • 96 R formats Each of the four framers contain dual two.
  • frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz 8.
  • bit parallel control port that can be used directly on either multiplexed or non.
  • multiplexed buses (Intel or Motorola) Extracts and inserts robbed bit signaling Detects and generates yellow (RAI).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS2-1Q4.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DS21Q42
Manufacturer Dallas Semiconducotr
File Size 1.28 MB
Description Enhanced QUAD T1 FRAMER
Datasheet download datasheet DS21Q42 Datasheet

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Other Datasheets by Dallas Semiconducotr

Part Number Description
DS21Q41B Quad T1 Framer
DS21Q43A Quad E1 Framer
DS21Q44 Enhanced QUAD E1 FRAMER
DS21Q48 5V E1/T1/J1 Line Interface
DS21Q348 3.3V E1/T1/J1 Line Interface

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS21Q42 Enhanced QUAD T1 FRAMER www.dalsemi.com FEATURES Four T1 DS1/ISDN–PRI/J1 framing transceivers All four framers are fully independent Each of the four framers contain dual two– frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz 8–bit parallel control port that can be used directly on either multiplexed or non– multiplexed buses (Intel or Motorola) Programmable output clocks for Fractional T1 Fully independent transmit and receive functionality Integral HDLC controller with 64-byte buffers configurable for FDL or DS0 operation Generates and detects in–band loop codes from 1 to 8 bits in length including CSU loop codes Pin compatible with DS21Q44 E1 Enhanced Quad E1 Framer 3.