Datasheet4U Logo Datasheet4U.com

3D3444 - MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

Description

The 3D3444 device is a small, versatile, quad 4-bit programmable monolithic delay line.

Delay values, programmed via the serial interface, can be independently varied over 15 equal steps.

The step size (in ns) is determined by the device dash number.

Features

  • Four indep’t programmable lines on a single chip All-silicon CMOS technology Low voltage operation (3.3V) Low quiescent current (1mA typical) Leading- and trailing-edge accuracy Vapor phase, IR and wave solderable Auto-insertable (DIP pkg. ) Increment range: 2ns through 25ns Delay tolerance: 1ns or 2% (See Table 1) Temperature stability: ±2% typical (0C-70C) Vdd stability: ±1% t.

📥 Download Datasheet

Datasheet preview – 3D3444

Datasheet Details

Part number 3D3444
Manufacturer Data Delay Devices
File Size 339.53 KB
Description MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
Datasheet download datasheet 3D3444 Datasheet
Additional preview pages of the 3D3444 datasheet.

📁 Similar Datasheet

Other Datasheets by Data Delay Devices
  • 3D3418 - MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE
  • 3D3424 - MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
  • 3D3428 - MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE
  • 3D3215 - MONOLITHIC 5-TAP 3.3V FIXED DELAY LINE
  • 3D3220 - MONOLITHIC 10-TAP FIXED DELAY LINE
  • 3D3225 - MONOLITHIC 5-TAP FIXED DELAY LINE
  • 3D3314 - MONOLITHIC QUAD FIXED DELAY LINE
  • 3D3323 - MONOLITHIC TRIPLE FIXED DELAY LINE

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com 3D3444 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444) FEATURES • • • • • • • • • • • • Four indep’t programmable lines on a single chip All-silicon CMOS technology Low voltage operation (3.3V) Low quiescent current (1mA typical) Leading- and trailing-edge accuracy Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Increment range: 2ns through 25ns Delay tolerance: 1ns or 2% (See Table 1) Temperature stability: ±2% typical (0C-70C) Vdd stability: ±1% typical Minimum input pulse width: 10% of total delay I1 SC I2 I3 I4 SI GND 1 2 3 4 5 6 7 PACKAGES 14 13 12 11 10 9 8 VDD AL O1 SO O2 O3 O4 I1 SC I2 I3 I4 SI GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD AL O1 SO O2 O3 O4 DIP-14 3D3444-xx SOIC-14 3D3444D-xx For mechanical dimensions, click here.
Published: |