PDU13F Datasheet | Data Delay Devices

FEATURES - - - - - - - - Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting Precise and stable delays Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability Fits standard 14-pin DIP socket Auto-insertable IN N/C N/C OUT OUT/ EN/ GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 data 3 delay devices, inc. PACKAGES VCC N/C N/C N/C A0 A1 A2 IN N/C N/C N/C OUT OUT/ EN/ GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9  VCC N/C N/C N/C A0 A1 A2 N/C PDU13F-xx PDU13F-xx A2 PDU13F-xx B2 PDU13F-xx M DIP Gull-Wing J-Lead Military DIP PDU13F-xx MC3 Military Gull-Wing FUNCTIONAL DESCRIPTION The PDU13F-series device is a 3-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A2-A0) according to the following formula: TDA = TD0 + TINC - A PIN DESCRIPTIONS IN OUT OUT/ A2 A1 A0 EN/ VCC GND Delay Line Input Non-inverted Output Inverted Output Address Bit 2 Address Bit 1 Address Bit 0 Output Enable +5 Volts Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (EN/) is held LOW during normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS - - - - - - - - Total programmed delay tolerance: 5% or 1ns, whichever is greater Inherent delay (TD0): 6ns typical (OUT) 5.5ns typical (OUT/) Setup time and propagation delay: Address to input setup (TAIS): 6ns Disable to output delay (TDISO): 6ns typ. (OUT) Operating temperature: 0° to 70° C Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VCC: 5VDC ± 5% Supply current: ICCH = 45ma ICCL = 20ma Minimum...