PDU17F Datasheet | Data Delay Devices

FEATURES - - - - - - - - N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC N/C A0 A1 A2 VCC N/C A3 A4 A5 VCC N/C N/C N/C N/C VCC N/C A6 N/C N/C data 3 ® delay devices, inc. PACKAGES OUT/ OUT EN/ GND N/C N/C N/C GND N/C N/C N/C N/C GND N/C EN/ N/C IN N/C GND Digitally programmable in 128 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting Precise and stable delays Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability Fits standard 40-pin DIP socket Auto-insertable PDU17F-xx DIP PDU17F-xx C5 Gull-Wing PDU17F-xx M Military DIP PDU17F-xx MC5 Military Gull-Wing FUNCTIONAL DESCRIPTION The PDU17F-series device is a 7-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A6-A0) according to the following formula: TDA = TD0 + TINC - A PIN DESCRIPTIONS IN OUT OUT/ A0-A6 EN/ VCC GND Delay Line Input Non-inverted Output Inverted Output Address Bits Output Enable +5 Volts Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS - - - - - - - - Programmed delay tolerance: 5% or 2ns, whichever is greater Inherent delay (TD0): 13ns typical (OUT) 12ns typical (OUT/) Setup time and propagation delay: Address to input setup (TAIS): 10ns Disable to output delay (TDISO): 6ns typ. (OUT) Operating temperature: 0° to 70° C Temperature...