PDJ2108DEBG - 2G bits DDR3 SDRAM

Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

PDJ2108DEBG 2g bits ddr3 sdram by Deutron Electronics - Datasheet Preview

Datasheet Details

Part number	PDJ2108DEBG
Manufacturer	Deutron Electronics
File Size	1.91 MB
Description	2G bits DDR3 SDRAM
Datasheet	PDJ2108DEBG Datasheet

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Other Datasheets by Deutron Electronics

Part Number	Description
PDJ2116DEBG	2G bits DDR3 SDRAM

Full PDF Text Transcription

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DATA SHEET 2G bits DDR3 SDRAM PDJ2108DEBG (256M words × 8 bits) PDJ2116DEBG (128M words × 16 bits) Specifications • Density: 2G bits • Organization: ⎯ 32M words × 8 bits × 8 banks (PDJ2108DEBG) ⎯ 16M words × 16 bits × 8 banks (EDJ2116DEBG) • Package: ⎯ 78-ball FBGA (PDJ2108DEBG) ⎯ 96-ball FBGA (PDJ2116DEBG) ⎯ Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V • Data rate ⎯ 1600Mbps/1333Mbps (max.

Published: Oct 17, 2014 |