PDJ2108DEBG Overview
DATA SHEET 2G bits DDR3 SDRAM PDJ2108DEBG (256M words × 8 bits) PDJ2116DEBG (128M words × 16 bits) Specifications Density: ⎯ 32M words × 8 bits × 8 banks (PDJ2108DEBG) ⎯ 16M words × 16 bits × 8 banks (EDJ2116DEBG) Package: ⎯ 78-ball FBGA (PDJ2108DEBG) ⎯ 96-ball FBGA (PDJ2116DEBG) ⎯ Lead-free (RoHS pliant) and Halogen-free Power supply:.
PDJ2108DEBG Key Features
- Double-data-rate architecture: two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better mand and data bus efficiency
- On-Die Termination (ODT) for better signal quality ⎯ Synchronous ODT ⎯ Dynamic ODT ⎯ Asynchronous ODT