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PDJ2116DEBG - 2G bits DDR3 SDRAM

Download the PDJ2116DEBG datasheet PDF. This datasheet also covers the PDJ2108DEBG variant, as both devices belong to the same 2g bits ddr3 sdram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Double-data-rate architecture: two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PDJ2108DEBG-DeutronElectronics.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PDJ2116DEBG
Manufacturer Deutron Electronics
File Size 1.91 MB
Description 2G bits DDR3 SDRAM
Datasheet download datasheet PDJ2116DEBG Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Deutron Electronics

Part Number Description
PDJ2108DEBG 2G bits DDR3 SDRAM

Full PDF Text Transcription

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DATA SHEET 2G bits DDR3 SDRAM PDJ2108DEBG (256M words × 8 bits) PDJ2116DEBG (128M words × 16 bits) Specifications • Density: 2G bits • Organization: ⎯ 32M words × 8 bits × 8 banks (PDJ2108DEBG) ⎯ 16M words × 16 bits × 8 banks (EDJ2116DEBG) • Package: ⎯ 78-ball FBGA (PDJ2108DEBG) ⎯ 96-ball FBGA (PDJ2116DEBG) ⎯ Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V • Data rate ⎯ 1600Mbps/1333Mbps (max.
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