DFPADD - Floating Point Pipelined Adder Unit

Product Overview

Digital Core Design

Datasheet Details

Part number	DFPADD
Manufacturer	Digital Core Design
File Size	151.46 KB
Description	Floating Point Pipelined Adder Unit
Datasheet	DFPADD Datasheet
Additional preview pages of the DFPADD datasheet.

Product details

Description

PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners.http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD Digital Core Design.

Features

Full IEEE-754 compliance Single precision real format support Simple interface No programming required 5 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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Published: Nov 9, 2008 |