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DFPADD Datasheet Floating Point Pipelined Adder Unit

Manufacturer: Digital Core Design

Overview: DFPADD .. Floating Point Pipelined Adder Unit ver 2.50 OVERVIEW ● Fully synthesizable, static synchronous design with no internal tri-states The DFPADD uses the pipelined mathematics algorithm to pute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports single precision real number. Add operation was pipelined up to 5 levels. Input data are fed every clock cycle. The first result appears after 5 clock periods latency and next results are available each clock cycle. Full IEEE754 precision and accuracy were included.

Datasheet Details

Part number DFPADD
Manufacturer Digital Core Design
File Size 151.46 KB
Description Floating Point Pipelined Adder Unit
Datasheet DFPADD_DigitalCoreDesign.pdf

Key Features

  • Full IEEE-754 compliance Single precision real format support Simple interface No programming required 5 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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