DFPADD Description
Floating Point Pipelined Adder Unit ver 2.50 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPADD uses the pipelined mathematics algorithm to pute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports single precision real number.
DFPADD Key Features
- Full IEEE-754 pliance Single precision real format support Simple interface No programming required 5 levels pipeline Fu
- Digital Core Design. All Rights Reserved
- performs input data analyze against IEEE-754 number standard pliance. The appropriate numbers and information about the
- performs floating point add function. Gives the plex