Description
PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input
Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag
Al
Features
- Full IEEE-754 compliance Single precision real format support Simple interface No programming required 5 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable
Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.
DFPADD Datasheet
