74AUP2G3404
Overview
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G3404 has one buffer and one inverter.
- Advanced Ultra Low Power (AUP) CMOS Supply Voltage Range from 0.8V to 3.6V ± 4mA Output Drive at 3.0V Low Static power consumption *
- ICC < 0.9µA CPD = 6pF Typical at 3.6V Low Dynamic Power Consumption Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The hysteresis is typically 250mV at VCC = 3.0V
- IOFF Supports Partial-Power-Down Mode Operation * * * * *
- ESD Protection per JESD 22 Exceeds 200-V Machine Model (A115) Exceeds 2000-V Human Body Model (A114-) Exceeds 1000-V Charged Device Model (C101)
