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74AUP2G3404 - Low-power buffer and inverter

General Description

The 74AUP2G3404 is a single buffer and single inverter.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Key Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial Power-down mode operation.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP2G3404 Low-power buffer and inverter Rev. 3 — 31 January 2022 Product data sheet 1. General description The 74AUP2G3404 is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Overvoltage tolerant inputs to 3.