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74LVC2G07 - DUAL BUFFERS

General Description

The 74LVC2G07 is a dual buffer gate with open drain outputs.

The device is designed for operation with a power supply range of 1.65V to 5.5V.

The input is tolerant to 5.5V allowing this device to be used in a mixed voltage environment.

Key Features

  • Wide Supply Voltage Range from 1.65V to 5.5V.
  • -24mA Output Drive at 3.0V.
  • CMOS Low Power Consumption.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • Inputs Accept up to 5.5V.
  • ESD Protection Tested per JESD 22.
  • Exceeds 200-V Machine Model (A115).
  • Exceeds 2000-V Human Body Model (A114).
  • Exceeds 1000-V Charged Device Model (C101).
  • Latch-Up Exceeds 100mA per JESD 78, Class I.
  • DFN1409 Package Designed as a Direct Replacement for Chip Scale Pac.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC2G07 DUAL BUFFERS WITH OPEN DRAIN OUTPUTS Description The 74LVC2G07 is a dual buffer gate with open drain outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The open-drain output can be connected to other open drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32mA. Features  Wide Supply Voltage Range from 1.65V to 5.5V  -24mA Output Drive at 3.