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74LVC2G07 - Buffers

General Description

The 74LVC2G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices.

This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Key Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • 5 V tolerant input/output for interfacing with 5 V logic.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B/JESD36 (2.7 V to 3.6 V).
  • 24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Latch-up performance exceeds 250 mA.
  • Direct interface with TTL levels.
  • Inpu.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET 74LVC2G07 Buffers with open-drain outputs Product specification Supersedes data of 2004 Mar 19 2004 Sep 08 Philips Semiconductors Product specification Buffers with open-drain outputs FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). • −24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V.