EM78P212N Overview
Each device in the series has as an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). Each provides a protection bit to prevent intrusion of user’s OTP memory code. Two Code option bits are also available to meet user’s requirements.
EM78P212N Key Features
- Features
- 2K×13 bits on-chip OTP-ROM
- 80×8 bits on-chip registers (SRAM)
- 8-level stacks for subroutine nesting
- 3 programmable Level Voltage Reset (LVR) : 4.0V, 3.0V, 2.5V
- Less than 1.5 mA at 5V/4MHz
- Typically 15 µA, at 3V/32kHz
- Typically 2 µA, during sleep mode
- I/O port configuration
- 4 bidirectional I/O ports: P5, P6, P7 and P8