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M12L2561616A - Synchronous DRAM

Datasheet Summary

Description

The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst Read single write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (8K cycle).
  • All Pb-free products are RoHS-Compli.

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Datasheet preview – M12L2561616A

Datasheet Details

Part number M12L2561616A
Manufacturer ESMT
File Size 1.66 MB
Description Synchronous DRAM
Datasheet download datasheet M12L2561616A Datasheet
Additional preview pages of the M12L2561616A datasheet.

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Full PDF Text Transcription

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ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)  All inputs are sampled at the positive going edge of the system clock  Burst Read single write operation  DQM for masking  Auto & self refresh  64ms refresh period (8K cycle)  All Pb-free products are RoHS-Compliant M12L2561616A (2T) 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L2561616A-5TG2T M12L2561616A-6TG2T M12L2561616A-7TG2T M12L2561616A-5BG2T M12L2561616A-6BG2T M12L2561616A-7BG2T Max Package Comments Freq.
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