M12L32321A-5BG2G Overview
The M12L32321A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for...
M12L32321A-5BG2G Key Features
- JEDEC standard 3.3V ± 0.3V power supply
- LVTTL patible with multiplexed address
- Dual banks operation
- MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
- All inputs are sampled at the positive going edge of the system clock
- Burst Read Single-bit Write operation
- DQM for masking