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M12L64164A-5TG2C - 1M x 16 Bit x 4 Banks Synchronous DRAM

This page provides the datasheet information for the M12L64164A-5TG2C, a member of the M12L64164A 1M x 16 Bit x 4 Banks Synchronous DRAM family.

Description

The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) - 15.6 µ s refresh interval M12L64164A (2C) 1M x 16 Bit x 4 Banks Synchronous DRAM.

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Datasheet preview – M12L64164A-5TG2C

Datasheet Details

Part number M12L64164A-5TG2C
Manufacturer ESMT
File Size 1.20 MB
Description 1M x 16 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L64164A-5TG2C Datasheet
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Full PDF Text Transcription

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ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) - 15.6 µ s refresh interval M12L64164A (2C) 1M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq.
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