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M12L64322A-6BG2S - 512K x 32 Bit x 4 Banks Synchronous DRAM

This page provides the datasheet information for the M12L64322A-6BG2S, a member of the M12L64322A 512K x 32 Bit x 4 Banks Synchronous DRAM family.

Description

The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L64322A (2S) 512K x 32 Bit x 4 Banks Synchronous DRAM.

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Datasheet preview – M12L64322A-6BG2S

Datasheet Details

Part number M12L64322A-6BG2S
Manufacturer ESMT
File Size 815.28 KB
Description 512K x 32 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L64322A-6BG2S Datasheet
Additional preview pages of the M12L64322A-6BG2S datasheet.

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Full PDF Text Transcription

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ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L64322A (2S) 512K x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq.
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