M13S5121632A Overview
Pin Name Function Pin Name Function A0~A12, BA0, BA1 Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP: Bank selects (4 Banks) DM is an input mask signal for write data. LDM, UDM LDM corresponds to the data on DQ0~DQ7;.
M13S5121632A Key Features
- Double-data-rate architecture, two data transfers per clock cycle
- Bi-directional data strobe (DQS)
- Differential clock inputs (CLK and CLK )
- DLL aligns DQ and DQS transition with CLK transition
- Four bank operation
- CAS Latency : 2, 2.5, 3
- Burst Type : Sequential and Interleave
- Burst Length : 2, 4, 8
- All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
- Data I/O transitions on both edges of data strobe (DQS)