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M15F2G16128A-BDBIG2B Datasheet 16m X 16 Bit X 8 Banks Ddr3 Sdram

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 pliant „ 8n Prefetch Architecture „ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) „ Double-data rate on DQs, DQS and DM z Data Integrity „ Auto Self Refresh (ASR) by DRAM built-in TS „ Auto Refresh and Self Refresh Modes z Power Saving Mode „ Power Down Mode z Signal Integrity „ Configurable DS for system patibility „ Configurable On-Die Termination „ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15F2G16128A (2B) Operation Temperature Condition -40°C~95°C 16M x 16 Bit x 8 Banks DDR3 SDRAM z Signal Synchronization 1 „ Write Leveling via MR settings „ Read Leveling via MPR z Programmable Functions „ CAS Latency (5/6/7/8/9/10/11/13) „ CAS Write Latency (5/6/7/8/9) „ Additive Latency (0/CL-1/CL-2) „ Write Recovery Time (5/6/7/8/10/12/14/16) „ Burst Type (Sequential/Interleaved) „ Burst Length (BL8/BC4/BC4 or 8 on the fly) „ Self Refresh Temperature Range(Normal/Extended) „ Output Driver Impedance (34/40) „ On-Die Termination of Rtt_Nom(20/30/40/60/120) „ On-Die Termination of Rtt_WR(60/120) „ Precharge Power Down (slow/fast) Note: 1. Only Support prime DQ’s feedback for each byte lane. Ordering Information Product ID Max Freq. M15F2G16128A –DEBIG2B M15F2G16128A –BDBIG2B 933MHz 800MHz VDD 1.5V 1.5V Data Rate (CL-tRCD-tRP) Package ments DDR3-1866 (13-13-13) 96 ball BGA Pb-free DDR3-1600 (11-11-11) 96 ball BGA Pb-free Elite Semiconductor Memory Technology Inc Publication Date : Aug. 2015 Revision : 1.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.

Key Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK 　falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. DDR3 SDRAM Addressing Configuration 128Mb x16 # of Bank 8 Bank Address BA0.

More Datasheets from ESMT (Elite Semiconductor Microelectronics Technology)

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