M15F2G16128A-DEBIG2B
Description
The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs.
Key Features
- SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS )
- Double-data rate on DQs, DQS and DM z Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes z Power Saving Mode
- Power Down Mode z Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
