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M15T1G1664A-EFBG2T Datasheet 8m X 16 Bit X 8 Banks Ddr3 Sdram

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT DDR3(L) SDRAM Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity ˗ Auto Refresh and Self Refresh Modes  Power Saving Mode ˗ Partial Array Self Refresh(PASR) ˗ Power Down Mode  Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15T1G1664A (2T) 8M x 16 Bit x 8 Banks DDR3(L) SDRAM  Signal Synchronization ˗ Write Leveling via MR settings ˗ Read Leveling via MPR  Programmable Functions ˗ CAS Latency (6/7/8/9/10/11/12/13/14) ˗ CAS Write Latency (5/6/7/8/9/10) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4/BC4 or 8 on the fly) ˗ Self Refresh Temperature Range(Normal/Extended) ˗ Output Driver Impedance (34/40) ˗ On-Die Termination of RTT_Nom(20/30/40/60/120) ˗ On-Die Termination of RTT_WR(60/120) ˗ Precharge Power Down (slow/fast) Table 1. Ordering Information Product ID Max Freq. VDD Data Rate (CL-tRCD-tRP) Package Comments M15T1G1664A–EFBG2T M15T1G1664A–DEBG2T 1066 MHz 933 MHz 1.35V / 1.5V 1.35V / 1.5V DDR3(L)-2133 (14-14-14) DDR3(L)-1866 (13-13-13) 96 ball BGA 96 ball BGA Pb-free Pb-free Elite Semiconductor Microelectronics Technology Inc Publication Date: Feb. 2025 Revision: 1.1 1/174 ESMT M15T1G1664A (2T) Contents Feature ...........................................................................................................................................................................................

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