M15T4G16256A-BDBG2S - DDR3 SDRAM

This page provides the datasheet information for the M15T4G16256A-BDBG2S, a member of the M15T4G16256A DDR3 SDRAM family.

Datasheet Summary

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight-bank DRAM.

The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 256Mb x 16 # of Bank 8 Bank Address BA0.

ESMT

Part number	M15T4G16256A-BDBG2S
Manufacturer	ESMT
File Size	8.07 MB
Description	DDR3 SDRAM
Datasheet	M15T4G16256A-BDBG2S Datasheet
Additional preview pages of the M15T4G16256A-BDBG2S datasheet.

Other Datasheets by ESMT

Click to expand full text

ESMT DDR3(L) SDRAM Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.

Published: Aug 19, 2025 |