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M15T4G16256A-EFBG2P Datasheet 32m X 16 Bit X 8 Banks Ddr3 Sdram

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT DDR3(L) SDRAM Feature  VDD = VDDQ = 1.35V (1.283–1.45V)  Backward-compatible to VDD = VDDQ = 1.5V ±0.075V  Differential bidirectional data strobe  8n-bit prefetch architecture  Differential clock inputs (CK, CK#)  8 internal banks  Nominal and dynamic on-die termination (ODT)  for data, strobe, and mask signals  Programmable CAS (READ) latency (CL)  Programmable posted CAS additive latency (AL)  Programmable CAS (WRITE) latency (CWL) M15T4G16256A (2P) 32M x 16 Bit x 8 Banks DDR3(L) SDRAM  Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])  Selectable BC4 or BL8 on-the-fly (OTF)  Self refresh mode  Self refresh temperature (SRT)  Automatic self refresh (ASR)  Write leveling  Multipurpose register  Output driver calibration Ordering Information Product ID Max Freq. VDD Data Rate (CL-tRCD-tRP) M15T4G16256A–EFBG2P 1066 MHz 1.35V / 1.5V DDR3(L)-2133 (14-14-14) M15T4G16256A–DEBG2P 933MHz 1.35V / 1.5V DDR3(L)-1866 (13-13-13) Package 96 ball BGA 96 ball BGA Comments Pb-free Pb-free Elite Semiconductor Microelectronics Technology Inc Publication Date: Aug. 2025 Revision: 1.

General Description

The 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device.

Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V compatible mode.

SDRAM Addressing Configuration # of Bank Bank Address Row Address Column Address Page size 256Mb x 16 8 BA0 – BA2 A0 – A14 A0 – A9 2KB Elite Semiconductor Microelectronics Technology Inc Publication Date: Aug.

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