M16U4G16256A-HHBG Datasheet | Elite Semiconductor Microelectronics Technology

Feature - Power supply - VDD = VDDQ = 1.2V ± 5% - VPP = 2.375V to 2.75V - 8 internal banks - 2 groups of 4 banks each (x16) - Differential clock inputs (CK_t and CK_c) - Bi-directional differential data strobe (DQS_t and DQS_c) - Asynchronous reset is supported (RESET_n) - ZQ calibration for Output driver by pare to external reference resistance (RZQ 240 ohm ±1%) - Nominal, park and dynamic On-die Termination (ODT) - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge - CAS Latency (CL): 9, 11, 12, 13, 14, 15, 16, 18,19, 20, 21, 22, 23 and 24 supported - Additive Latency (AL) 0, CL-1, and CL-2 supported - Burst Length (BL): 8 and 4 with on the fly supported - CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16, 18 and 20 supported - Refresh cycles Average refresh period - 7.8μs at 0°C ≤ TC ≤ +85°C - 3.9μs at +85°C < TC ≤ +95°C - Fine granularity refresh is supported - Adjustable internal generation VREFDQ - Pseudo Open Drain (POD) interface for data input/output - Driver strength selected by MRS - The high-speed data transfer by the 8 bits prefetch - Temperature Controlled Refresh (TCR) mode is supported - Low Power Auto Self Refresh (LPASR) mode is supported - Self-refresh abort is supported - Programmable preamble is supported - Write leveling is supported - mand/Address latency (CAL) is supported - Multipurpose register READ and WRITE capability - mand Address (CA) Parity for mand/address signal error detect and inform it to controller - Write Cyclic Redundancy Code (CRC) for DQ error detect and inform it to controller during high-speed operation - Data Bus Inversion (DBI) for Improve the power consumption and signal integrity of the memory interface (x16 product only) - Data Mask (DM) for write data - Per DRAM Addressability (PDA) for each DRAM can be set a different mode register value individually and has individual...