Datasheet Summary
ESMT
M54D1G1664A (2G)
LPDDR2 SDRAM
8M x 16 Bit x 8 Banks LPDDR2 SDRAM
Feature
- JEDEC LPDDR2‐S4B pliance
- HSUL_12 interface (High Speed Unterminated Logic 1.2V)
- Power supply
- VDD1 = 1.7 to 1.95V
- VDD2, VDDCA, VDDQ = 1.14 to 1.3V
- 4n prefetch architecture
- Multiplexed, double data rate, mand/address inputs; mands entered on every CK edge
- Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)
- Programmable read latency (RL) and write latency (WL)
- Programmable burst lengths (BL): 4, 8, 16
- Pre-bank refresh for concurrent operation
- Partial Array Self Refresh (PASR)
- Temperature pensated Self Refresh (TCSR) by built‐in temperature sensor
- Deep...