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M54D2G16128A - LPDDR2 SDRAM

Description

Function Clock: CK_t and CK_c are differential clock inputs.

All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t.

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Datasheet Details

Part number M54D2G16128A
Manufacturer ESMT
File Size 5.71 MB
Description LPDDR2 SDRAM
Datasheet download datasheet M54D2G16128A Datasheet

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    Full PDF Text Transcription

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    ESMT M54D2G16128A LPDDR2 SDRAM 16M x 16 Bit x 8 Banks LPDDR2 SDRAM Feature  JEDEC LPDDR2‐S4B compliance  HSUL_12 interface (High Speed Unterminated Logic 1.2V)  Power supply: - VDD1 = 1.7 to 1.95V - VDD2, VDDCA, VDDQ = 1.14 to 1.
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