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M55D4G32128A-GFBG2R - 16M x 32 Bit x 8 Banks LPDDR3 SDRAM

General Description

Function Clock: CK_t and CK_c are differential clock inputs.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT LPDDR3 SDRAM Feature  Ultra-low-voltage core and I/O power supplies ­ VDD1 = 1.70–1.95V ­ VDD2, VDDCA, VDDQ = 1.14–1.