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M56Z4G16256A-TNBYG2H - 32M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM

Download the M56Z4G16256A-TNBYG2H datasheet PDF. This datasheet also covers the M56Z4G16256A-SMBYG2H variant, as both devices belong to the same 32m x 16 bit x 8 banks lpddr4/lpddr4x sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

Clock: CK_t and CK_c are differential clock inputs.

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Note: The manufacturer provides a single datasheet file (M56Z4G16256A-SMBYG2H-ESMT.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M56Z4G16256A-SMBYG2H 32M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z4G32128A-SMBYG2R 16M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z4G32128A-TNBYG2R 16M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z2G16128A-SMBYG2R 16M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z2G16128A-TNBYG2R 16M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT M56Z4G16256A (2H) LPDDR4/LPDDR4X SDRAM 32M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM Feature  Ultra-low-voltage core and I/O power supply – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal – VDDQ = 1.06–1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal  Array configuration – 256 Meg × 16 (1 channel ×16 I/O)  Device configuration – 256M16 × 1 die in package  16n prefetch DDR architecture  8 internal banks per channel for concurrent operation  Single-data-rate CMD/ADR entry  Bidirectional/differential data strobe per byte lane  Programmable READ and WRITE latencies (RL/WL)  Programmable and on-the-fly burst lengths (BL = 16, 32)  Directed per-bank refresh for concurrent bank operation and ease of command scheduling  Up to 8.