Overview: HM63921 Series
2048-word × 9-bit CMOS Parallel In-Out FIFO Memory The HM63921 is a first-in, first-out memory that utilizes a high performance static RAM array with internal algorithm that controls, monitors and declares status of the memory by empty flag, full flag and half-full flag, to prevent data overflow or underflow. Expansion logic warrants unlimited expansion capability in width and depth. Both read and write are independent from each other and their corresponding pointers are designed to select the proper locations out of the entire array serially without address information to load or unload data. Data is toggled in and out of the device through the use of the write enable (W) and read enable (R) pins. The device has a read/write cycle time of 30/35/45 ns. Organization of HM63921 provides a 9-bit data bus. The ninth bit could be used for control or parity for error checking at the option of the user. The HM63921 is fabricated using the Hitachi CMOS 1.3 micron technology. The device is available in DIP and SOJ.
