P4C188 Datasheet | Unknown Manufacturer

FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 10/12/15/20/25 ns (mercial) - 12/15/20/25/35 (Industrial) - 15/20/25/35/45 ns (Military) Low Power (mercial/Military) - 715 m W Active - 12/15 - 550/660 m W Active - 20/25/35/45 - 193/220 m W Standby (TTL Input) - 83/110 m W Standby (CMOS Input) P4C188 - 15 m W Standby (CMOS Input) (P4C188L Military) Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C188L Military) Three-State Outputs TTL/CMOS patible Outputs Fully TTL patible Inputs Standard Pinout (JEDEC Approved) - 22-Pin 300 mil DIP - 24-Pin 300 mil SOJ - 22-Pin 290 x 490 mil LCC DESCRIPTION The P4C188 and P4C188L are 65,536-bit ultra high speed static RAMs organized as 16K x 4. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs and outputs are fully TTL-patible. The RAMs operate from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption to a low 715m W active, 193m W standby and only 5m W in the P4C188L version. The P4C188 and P4C188L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ and 22-pin LCC packages providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM A (8) A I/O 1 I/O 2 I/O 3 I/O 4 ROW SELECT 65,536-BIT MEMORY ARRAY PIN CONFIGURATIONS V CC 22 1 A0 A1 A2 A3 A4 A5 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 V CC A 13 A 12 A 11 A 10 A9 I/O 4 I/O 3 I/O 2 I/O 1 WE A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 10 11 12 A 13 21 20 19 18 17 16 15 14 13 A1 A0 A 12 A 11 A 10 A9 I/O 4 I/O 3 I/O 2 INPUT DATA CONTROL COLUMN I/O A6 A7 A8 CE GND COLUMN SELECT CE A (6) WE A DIP (P3, D3) TOP...