P4C198 Datasheet | Unknown Manufacturer

FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 10/12/15/20/25 ns (mercial) - 12/15/20/25/35 ns (Industrial) - 15/20/25/35/45 ns (Military) Low Power Operation (mercial/Military) - 715 m W Active - 12/15 - 550/660 m W Active - 20/25/35/45/55 - 193/220 m W Standby (TTL Input) - 83/110 m W Standby (CMOS Input) P4C198/198A - 9 m W Standby (CMOS Input) P4C198L/198AL (Military) 5V ± 10% Power Supply Data Retention, 10 µA Typical Current from 2.0V P4C198L/198AL (Military) Output Enable & Chip Enable Control Functions - Single Chip Enable P4C198 - Dual Chip Enable P4C198A mon Inputs and Outputs Fully TTL patible Inputs and Outputs Standard Pinout (JEDEC Approved) - 24-Pin 300 mil DIP - 24-Pin 300 mil SOJ (P4C198 only) - 28-Pin 350 x 550 mil LCC (P4C198 only) DESCRIPTION The P4C198/L and P4C198A/L are 65,536-bit ultra highspeed static RAMs organized as 16K x 4. Each device features an active low Output Enable control to eliminate data bus contention. The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables, both active low) for easy system expansion. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-patible. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 715 m W active, 193 m W standby. The P4C198/L and P4C198A/L are available in 24-pin 300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM A (8) A I/O 1 I/O 2 I/O 3 I/O 4 INPUT DATA CONTROL COLUMN I/O ROW SELECT 65,536-BIT MEMORY ARRAY PIN CONFIGURATIONS A0 A1 A2 A3 A4 A5 A6 A7 A8 C E (C E 1) OE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14...