P4C1981L Datasheet PDF

PYRAMID P4C1981L

The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4) ultra high-speed static RAMs similar to the P4C198, but with separate data I/O pins. The P4C1981/L feature a transparent write operation when OE is low; the outputs of the P4C1982/L are in high impedance during the write cycle. The RAMs operate from a single 5V ± 10% tolerance power supply.

Part No.	P4C1981L
Datasheet	P4C1981L Download
Manufacturer	PYRAMID
Description	STATIC CMOS RAM
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FEATURES

Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation (Commercial/Military) Output Enable and Dual Chip Enable Functions 5V ± 10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C1981L/1982L Military) Separate Inputs and Outputs – P4C1981/L Input Data at Outputs during Write – P4C1982/L Outputs in High Z during Write Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC – 28-Pin CERPACK

DESCRIPTION

All devices have low power standby modes. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from 2.0V supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption. For the P4C1982L and P4C1981L, power is only 5.5 mW standby with CMOS input levels.