PA7024 Datasheet | Unknown Manufacturer

Features s CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground patibility Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Flexible Logic Cell - Multiple output functions per cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables -Sum of products logic for output enable s High-Speed mercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (f MAX) - Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85°C temperatures Ideal for binatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, plex state-machines - parators, decoders, multiplexers and other wide-gate functions Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software -Programming support by ICT PDS-3 and popular thirdparty programmers s s s s General Description The PA7024 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7024 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40 registers/latches (20 buried logic cells and 20 I/O registers/latches). Its logic array implements 84 sum-of-product logic functions that share 80 product terms. The PA7024’s logic and I/O cells (LCCs, IOCs) are extremely flexible, offering two output functions per logic cell (a total of 40 for all 20 logic cells). Logic cells are configurable as D, T, and JK...