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PA7024 - Programmable Electrically Erasable Logic Array

Download the PA7024 datasheet PDF. This datasheet also covers the PA7 variant, as both devices belong to the same programmable electrically erasable logic array family and are provided as variant models within a single manufacturer datasheet.

General Description

The PA7024 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

Key Features

  • s CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground compatibility Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Flexible Logic Cell - Multiple output functions per cell - D,T and JK registers with special features - Independent or global.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PA7-024.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PA7024
Manufacturer Unknown Manufacturer
File Size 427.05 KB
Description Programmable Electrically Erasable Logic Array
Datasheet download datasheet PA7024 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Commercial/ Industrial PA7024 PA7024 PEELTM Array Programmable Electrically Erasable Logic Array Features s CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground compatibility Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Flexible Logic Cell - Multiple output functions per cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables -Sum of products logic for output enable s High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.