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PA7024 Datasheet

Programmable Electrically Erasable Logic Array

Manufacturer: Unknown Manufacturer

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number PA7024
Manufacturer Unknown Manufacturer
File Size 427.05 KB
Description Programmable Electrically Erasable Logic Array
Datasheet PA7024 PA7 Datasheet (PDF)

PA7024 Overview

The PA7024 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7024 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40...

PA7024 Key Features

  • Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground patibility Most
  • 20 I/Os, 2 inputs/clocks, 40 registers/latches
  • 40 logic cell output functions
  • PLA structure with true product-term sharing
  • Logic functions and registers can be I/O-buried Flexible Logic Cell
  • Multiple output functions per cell
  • D,T and JK registers with special features
  • Independent or global clocks, resets, presets, clock polarity and output enables -Sum of products logic for output enabl
  • As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
  • Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85°C temperatures Ideal for binatorial, Synchronous and Async

PA7024 Distributor