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PA7540 - PA7540 PEEL Array Programmable Electrically Erasable Logic

This page provides the datasheet information for the PA7540, a member of the PA7 PA7540 PEEL Array Programmable Electrically Erasable Logic family.

Datasheet Summary

Description

The PA7540 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

Features

  • - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - Anachip’s WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers presets, clock polarity, and other features, making the PA7540 suitable for a variety of combinatorial, synchronous and asynchronous logic.

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Datasheet preview – PA7540

Datasheet Details

Part number PA7540
Manufacturer ETC
File Size 239.25 KB
Description PA7540 PEEL Array Programmable Electrically Erasable Logic
Datasheet download datasheet PA7540 Datasheet
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Full PDF Text Transcription

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PA7540 PEEL Array™ Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other widegate functions High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX) - Industrial grade available for 4.5 to 5.
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