PALCE600 Datasheet | Unknown Manufacturer

USE GAL DEVICES FOR NEW DESIGNS FINAL ’L: H-15/25 CONNECTION DIAGRAMS Top View SKINNYDIP I/O9 PLCC/LCC CLK1 VCC I I I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I CLK2 12950G-2 EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS s Lattice/Vantis Programmable Array Logic (PAL) architecture s Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed - -15 = 15-ns tPD - -25 = 25-ns tPD s Sixteen macrocells with configurable I/O architecture s Registered or binatorial operation s Registers programmable as D, T, J-K, or S-R s Asynchronous clocking via product term or bank register clocking from external pins s Register preload for...