QL2009-0PB256I Overview
3.3V and 5.0V pASIC 2 FPGA bining Speed, Density, Low Cost and Flexibility Rev.
QL2009-0PB256I Key Features
- 3.3V and 5.0V operation with low standby power -I/O pin-patibility between different devices in the same packages -PCI p
- 217 bidirectional input/output pins, PCI-pliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
- Two array networks available to logic cell flip-flop clock, set, and reset
- each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O
- each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback