Datasheet4U Logo Datasheet4U.com

QL2003 - Low Cost and Flexibility

Description

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d

Features

  • -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2003 Block Diagram 192 Logic Cells 3-5 QL2003.

📥 Download Datasheet

Datasheet preview – QL2003

Datasheet Details

Part number QL2003
Manufacturer QL
File Size 236.38 KB
Description Low Cost and Flexibility
Datasheet download datasheet QL2003 Datasheet
Additional preview pages of the QL2003 datasheet.

📁 Similar Datasheet

  • QL2007 - pASIC 2 FPGA Combining Speed (ETC)
  • QL2009 - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PB256C - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PB256I - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PF144C - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PF144I - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PQ208C - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-0PQ208I - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-1PB256C - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
  • QL2009-1PB256I - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility (ETC)
Other Datasheets by QL

    Full PDF Text Transcription

    Click to expand full text
    www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.
    Published: |