QL2007 Datasheet

Manufacturer: Unknown Manufacturer

Datasheet Details

3.3V and 5.0V pASIC 2 FPGA bining Speed, Density, Low Cost and Flexibility Rev.

3.3V and 5.0V operation with low standby power -I/O pin-patibility between different devices in the same packages -PCI p
166 bidirectional input/output pins, PCI-pliant at 5.0V in -1/-2 speed grades
4 high-drive input-only pins
4 high-drive input/distributed network pins
Two array networks available to logic cell flip-flop clock, set, and reset
each driven by an input-only pin
Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O
each driven by an input-only pin, or any input or

Part Number	Description
QL2009	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PB256C	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PB256I	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PF144C	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PF144I	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PQ208C	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-0PQ208I	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-1PB256C	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-1PB256I	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-1PF144C	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility