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QL2007 - pASIC 2 FPGA Combining Speed

Description

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d

Features

  • -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram 480 Logic Cells 3-25 DataSheet 4 U . com www. DataSheet4U. com QL2007.

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Datasheet Details

Part number QL2007
Manufacturer ETC
File Size 331.88 KB
Description pASIC 2 FPGA Combining Speed
Datasheet download datasheet QL2007 Datasheet
Additional preview pages of the QL2007 datasheet.

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www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.
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