QL2009-0PQ208C Datasheet | Unknown Manufacturer

3.3V and 5.0V p ASIC 2 FPGA bining Speed, Density, Low Cost and Flexibility Rev. C p ASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 9,000 usable ASIC gates, 225 I/O pins -16-bit counter speeds exceeding 200 MHz -9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os -3-layer metal Via Link® process for small die sizes -100% routable and pin-out maintainable 3 p ASIC 2 Advanced Logic Cell and I/O Capabilities -plex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins Other Important Family Features -3.3V and 5.0V operation with low standby power -I/O pin-patibility between different devices in the same packages -PCI pliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of the p ASIC 2 family of FPGAs. p ASIC 2 FPGAs employ a unique bination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make p ASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics. The QL2009 contains 672 logic cells. With 225 maximum I/Os, the QL2009 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages. Software support for the plete p ASIC families, including the QL2009, is available through three basic packages. The turnkey Quick Works®...