QL2009-0PF144C Overview
3.3V and 5.0V pASIC 2 FPGA bining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 9,000 usable ASIC gates, 225 I/O pins pASIC 2 Advanced Logic Cell and I/O Capabilities -plex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins Other Important Family Features - 217 bidirectional input/output pins, PCI-pliant at 5.0V in -1/-2 speed grades - 4 high-drive input-only pins - 4 high-drive input/distributed...
QL2009-0PF144C Key Features
- 3.3V and 5.0V operation with low standby power -I/O pin-patibility between different devices in the same packages -PCI p
- 217 bidirectional input/output pins, PCI-pliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
- Two array networks available to logic cell flip-flop clock, set, and reset
- each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O
- each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback