SDA9401 - Scan Rate Converter using Embedded DRAM Technology Units
General Description
4
Key Features
nput data formats - 4:2:2 luminance and chrominance parallel (2 x 8 wires) - ITU-R 656 data format (8 wires) Two different representations of input chrominance data - 2‘s complement code - Positive dual code Flexible input sync controller Flexible compression of the input signal - Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - Digital horizontal compression of the input signal (1.0, 2.0, 4.0) Noise reduction - Motion adaptive spatial and temporal noise r.
Full PDF Text Transcription for SDA9401 (Reference)
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SDA9401. For precise diagrams, and layout, please refer to the original PDF.
PRELIMINARY DATA SHEET SDA 9401 SCARABAEUS Scan Rate Converter using Embedded DRAM Technology Units Edition Feb. 28, 2001 6251-558-1PD Document Change Note DS1 Date Secti...
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Edition Feb. 28, 2001 6251-558-1PD Document Change Note DS1 Date Section/ Page Changes compared to previous issue Department 25.09.98 05.05.99 01.07.99 page 61 page 20 Changes to previous issue Version 0, Edition 05/98 HL IV CE are marked with a changebar ESD model CDM added, -1.5 kV, ..., 1,5 kV IV CE In Multipicture mode only STOPMODE = 0110 pos- IV CE sible Preliminary Data Sheet Version 01, Edition 04/00 CNP HN PD update new logo, removal of change bars 26.04.00 all 1)... DS = Document state, compares to block 4 of document number Micronas 2 Preliminary Data Sheet SDA 9401 List of Tables 1 2 3 4 5 Page General descript
SDA9401 Datasheet
