SMJ44400 Datasheet | Unknown Manufacturer

FEATURES - Organized 1,048,576 x 4 - Single +5V ±10% power supply - Enhanced Page-Mode operation for faster memory access P Higher data bandwidth than conventional page-mode parts P Random Single-Bit Access within a row with a column address - CAS-Before-RAS (CBR) Refresh - Long Refresh period: 1024-cycle Refresh in 16ms (Max) - 3-State unlatched Output - Low Power Dissipation - All Inputs/Outputs and Clocks are TTL patible - Processing to MIL-STD-883, Class B available Pin Name A0 - A9 CAS DQ1 - DQ4 OE RAS W Vcc Vss Function Address Inputs Column-Address Strobe Data Inputs/Outputs Output Enable Row-Address Strobe Write Enable 5V Supply Ground OPTIONS - Timing 80ns access 100ns access 120ns access - Package(s) Ceramic DIP (400mils) Ceramic Flatpack MARKING -80 -10 -12 The SMJ44400 is offered in a 400-mil, 20-pin ceramic side-brazed dual-in-line package (JD suffix) and a 20-pin ceramic flatpack (HR suffix) that are characterized for operation from -55°C to +125°C. OPERATION JD HR No. 113 No. 308 Enhanced Page Mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses A0 through A9 can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the columnaddress buffers in this device are activated on the - Operating Temperature Ranges M Military (-55o C to +125o C) GENERAL DESCRIPTION The SMJ44400 is a series of 4,194,304-bit dynamic random-access memories (DRAMs), organized as 1,048,576 words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and low-power operation. The SMJ44400 features maximum row access times of 80ns, 100ns, and...