M13S128168A Datasheet | Elite Semiconductor Memory Technology

ESMT M13S128168A (2S) DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features - Double-data-rate architecture, two data transfers per clock cycle - Bi-directional data strobe (DQS) - Differential clock inputs (CLK and CLK ) - DLL aligns DQ and DQS transition with CLK transition - Four bank operation - CAS Latency : 2, 2.5, 3 - Burst Type : Sequential and Interleave - Burst Length : 2, 4, 8 - All inputs except data & DM are sampled at the rising edge of the system clock (CLK) - Data I/O transitions on both edges of data strobe (DQS) - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Data mask (DM) for write masking only - VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V - 15.6us refresh interval - Auto & Self refresh - 2.5V I/O (SSTL_2 patible) Ordering Information Product ID Max Freq. M13S128168A-4TG2S M13S128168A-4.5TG2S - 1 250MHz (DDR500) 225MHz (DDR450) M13S128168A-5TG2S 200MHz (DDR400) M13S128168A-6TG2S...