F50L512M41A Overview
The serial electrical interface follows the industry-standard serial peripheral interface (SPI), providing a cost-effective non-volatile memory storage solution in systems where pin count must be kept to a minimum. The device is a 512Mb SLC SPI-NAND Flash memory device based on the standard parallel NAND Flash, but new mand protocols and registers are defined for SPI operation. It is also an alternative to SPI-NOR,...
F50L512M41A Key Features
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
- Page Size: (2K + 64) Byte
- Read from Cell to Register with Internal ECC: 100us
- Program time:400us
- Block Erase time: 4ms
- Program/Erase Lockout During Power Transitions
- Internal ECC Requirement: 1bit/512Byte