DESCRIPTION
Elixir 512Mb SDRAMs is a high-speed CMOS Double Data Rate SDRAM containing 536,870,912 bits. It is internally configured as a qual-bank DRAM. The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2η prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 512Mb DDR SDRAM operates from a differential clock (CK and ; the crossing of CK going high and going LOW is referred to as the positive edge of CK).
Elixir
