EBD52UC8AKFA-5 Overview
The EBD52UC8AKFA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
EBD52UC8AKFA-5 Key Features
- 184-pin socket type dual in line memory module (DIMM) PCB height: 31.75mm Lead pitch: 1.27mm
- 2.5V power supply
- Data rate: 400Mbps (max.)
- 2.5 V (SSTL_2 patible) I/O
- Double Data Rate architecture; two data transfers per clock cycle
- Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver
- Data inputs and outputs are synchronized with DQS
- 4 internal banks for concurrent operation (ponent)
- DQS is edge aligned with data for READs; center aligned with data for WRITEs
- Differential clock inputs (CK and /CK)