EBD52UC8AKDA Overview
The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
EBD52UC8AKDA Key Features
- 200-pin socket type small outline dual in line memory module (SO DIMM) PCB height: 31.75mm Lead pitch: 0.6mm
- 2.5V power supply
- Data rate: 333Mbps/266Mbps (max.)
- 2.5 V (SSTL_2 patible) I/O
- Double Data Rate architecture; two data transfers per clock cycle
- Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver
- Data inputs, outputs and DM are synchronized with DQS
- 4 internal banks for concurrent operation (ponent)
- DQS is edge aligned with data for READs; center aligned with data for WRITEs
- Differential clock inputs (CK and /CK)