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EDD5108ABTA - 512M bits DDR SDRAM

General Description

The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words × 4 bits × 4 banks.

The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words × 8 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

Key Features

  • 2.5 V power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V.
  • Data Rate: 333Mbps/266Mbps (max. ).
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • 4 internal banks for concurrent operation.
  • DQS is edge aligned with data for READs; center aligned wit.

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Datasheet Details

Part number EDD5108ABTA
Manufacturer Elpida Memory
File Size 444.40 KB
Description 512M bits DDR SDRAM
Datasheet download datasheet EDD5108ABTA Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY DATA SHEET 512M bits DDR SDRAM EDD5104ABTA (128M words × 4 bits) EDD5108ABTA (64M words × 8 bits) Description The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words × 8 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66-pin plastic TSOP (II)10.16mm(400).