EDD5108AFTA Overview
Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
EDD5108AFTA Key Features
- Power supply: VDD, VDDQ = 2.5V ± 0.2V
- Data Rate: 333Mbps/266Mbps (max.)
- Double Data Rate architecture; two data transfers per clock cycle
- Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
- Data inputs, outputs, and DM are synchronized with DQS
- 4 internal banks for concurrent operation
- DQS is edge aligned with data for READs; center aligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS