EDD5108AGTA Overview
DATA SHEET 512M bits DDR SDRAM EDD5108AGTA (64M words × 8 bits) EDD5116AGTA (32M words × 16 bits) Specifications Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS pliant) Power supply:.
EDD5108AGTA Key Features
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
- Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
- Data inputs, outputs, and DM are synchronized with DQS
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data