EDE5104AESK - (EDE510xAESK) 512M bits DDR2 SDRAM

This page provides the datasheet information for the EDE5104AESK, a member of the EDE5108AESK (EDE510xAESK) 512M bits DDR2 SDRAM family.

Product Overview

Elpida Memory

Part number	EDE5104AESK
Manufacturer	Elpida Memory
File Size	680.50 KB
Description	(EDE510xAESK) 512M bits DDR2 SDRAM
Datasheet	EDE5104AESK Datasheet
Additional preview pages of the EDE5104AESK datasheet.

The EDE5104AESK is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks.

The EDE5108AESK is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks.

They are packaged in 60-ball FBGA (µBGA) package.

Power supply: VDD, VDDQ = 1.8V ± 0.1V.
Double-data-rate architecture: two data transfers per clock cycle.
Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver.
DQS is edge aligned with data for READs: centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on e.

Other Datasheets by Elpida Memory

Published: Mar 13, 2006 |