EDE5104AESK Overview
The EDE5104AESK is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDE5108AESK is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks. They are packaged in 60-ball FBGA (µBGA) package.
EDE5104AESK Key Features
- Power supply: VDD, VDDQ = 1.8V ± 0.1V
- Double-data-rate architecture: two data transfers per clock cycle
- Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data
- DQS is edge aligned with data for READs: centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge: data and data mask referenced to both edges of DQS
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- Burst lengths: 4, 8